The JEDEC (Solid State Technologies Alliance) has introduced a new generation of UFS 3.1 slots with new features including improved performance and reduced prices and increased stability compared to the previous generation.
These new capabilities promise to improve device performance and minimize power consumption and improve the user experience. Also, the cost savings have been so high that in the future, the use of these memory devices can be seen in mid-range devices, in addition to flagships.
UFS 3.1-compliant devices will continue to support the physical layer of M-PHY, like the previous generation, but this standard has been upgraded from M-PHY 4 to M-PHY 4.1. M-PHY 4.1 is a physical layer embedded in data transmission equipment developed by the MIPI Alliance, which handles raw bits with 8b / 10b linear encoding and 2.5GB bandwidth per line.
In this release, we are adding three important features of Write Booster, Deep Sleep,
and Performance Throttling Notification, features that are currently available on market-flagged SSDs . In fact, JEDEC is trying to get UFS 3.1 memory closer to SSDs in terms of performance.
The Write Booster technology is designed to accelerate write speeds using pseudo-SLC cache memory,
a technology seen in SSMs and NVMe memory used on small devices, including the Apple iPhone and iPad .
Price Reduction and Optimal UFS 3.1 Memory Usage Allows Using it in Short Term Devices
The second important feature added is called Deep Sleep and is specifically designed for low-cost devices
that do not have a separate voltage regulator for memory. Thanks to this technology, it is possible to share electricity from the voltage regulator elsewhere to the UFS 3.1 memory. This indicates a very low consumption of new memory, which ultimately increases the battery life of the device.
Performance Throttling Notification, “throat-aware notification of performance”,
enables UFS 3.1 memory to reduce memory pressure if the temperature rises
and warns the host device to prevent this from happening in the future. Prevention of throat formation means more stable performance.
Not to mention the new HP Performance Host Booster standard introduced by JEDEC. Since mobile software requires a large amount of random data to read, it is difficult to maintain this growing amount of data in the controller memory and requires more cache memory in the UFS memory controller, which naturally increases costs.
Host Performance Booster enables UFS memory to cache portions of its data on the host device’s DRAM memory.
This will reduce the cost of building a memory controller in addition to speeding up the read speed of the data.
Samsung, which has been using HPB on its SSDs for many years,
claims to have a 5 percent faster read speed of random data. It goes without saying that HPB is not mandatory and can be used based on the need and the decision maker.
Compare the performance of UFS 2.1 with UFS 3
According to the specifications,
the bandwidth of UFS 3.1 memory in theory reaches to 1.5 Gb / s (1.5 Gb / s)
which in actual operating conditions can be estimating to be about 2.5 Gb / s,
according to the encoding uses in M-PHY 4.1. Of course, if you use HPB, this is an increase.
While many flagships last year used UFS 2.1 generation memory,
the OnePlus 2 , Galaxy F2 , Relay X2 Pro and Galaxy Note 2 were equip with UFS 3. One of the first UFS 3.1 handsets to mention the Galaxy S 20 and OnePlus 2. In the end, it’s interesting to note that Apple has not used the UFS memory in the iPhone so far and has preferred NVMe memory.